Implementation of SAD Architecture for Motion Estimation in H.264/AVC
نویسنده
چکیده
Abstract— The last decade has seen a quiet uprising in digital video technology. The digital videos are been used in television, broadcasting, Internet and also in mobile phones. The uprising issues use H.264/AVC formats in video compression techniques. The SAD operation can be divided into two stages, viz. absolute and sum stage. Pipelining method is implemented as it is used in low power applications like mobile devices. For checking the functionality, HDL verification is done by using ModelSim Simulator. This paper represents the idea of yielding a faster outcome than real-time Full-Search (FS) in Motion Estimation (ME) for the main profile/main level of the H.264 standard. In order to generate the outcomes, we use TSMC 45 nm standard-cells library by using Cadence RTL Compiler tool and the obtained frequency of about 176.05 MHz. KeywordHardware Description Language (HDL), Sum of Absolute Difference (SAD), Advanced Video Coding (AVC).
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